CSE1CT Computer Technology

Virtual Memory


Introduction

Virtual memory was originally a scheme to make the CPU "think" it had more RAM connected than it actually had.

The basic idea was that addresses issued by the CPU would be checked before trying to access memory. If the address was for some Real RAM®, the access was allowed. If the address referred to an unimplemented part of memory, the users program was suspended and memory management hardware (and software) fetched the requested things from disc. The users program was then resumed, but with the address modified to point at the newly updated area.

Diagram.CPU issues a logical address. This address is modified by the memory manager. It replaces the higher bits in the address with bits looked up in a table. In effect the memory manager relocates pieces of RAM. Each piece can be marked with protection attributes. End of diagram

One side effect of this was that the memory visible from the CPU could be controlled. All areas could be marked as present (or absent), read only, readable and writable, or access could be denied completely.

The original idea of faking larger memory is still with us in the form of "swap" space (a place to put inactive pieces of code and data till they are required) BUT swapping is very slow.

The access control provided by virtual memory is the main reason it is used now - it protects programs from one another.


Virtual memory relies on the Principle of Locality:

In general, programs tend to cause patterns of localised memory accesses.

This leads to the observation that only a few pages will be accessed frequently while others will be accessed infrequently.


Types of VM

There are two main types. Segmented VM and Paged VM. The 386 and all later Intel® CPU can implement both types (singly or together)

Segmented VM

A memory address is made of two parts: The segment registers contained three fields:
Diagram. The segment register holds 16 bits. 13 are an index, one is a table indicator. Two are used to indicate priority level. The table indicator bit selects one of two tables (local to task or global to all). The index is used to select one descriptor from the selected table. End of diagram

The descriptor accessed (by the segment register when it is loaded) returned the following information:

This information is held (cached if you like) in a hidden table in the CPU. This saves the CPU accessing the descriptor tables for every memory access.

This information allowed the CPU to access a segment (from one byte to a megabyte long) located anywhere in memory.

Diagram. Memory address equals base address plus index. End of diagram

The segment could be marked as readable and writable, read only or access could be blocked. Any attempt by a program to "do the wrong thing" could be detected and the program terminated before any damage was done.


Paged VM

The logical address issued by the CPU is split into two parts.

Diagram. Most significant part of the logical address (also called the logical page) selects an entry from the page table. This entry provides the physical page number. The Physical address equals the physical page number concatenated with (joined to) the logical offset. End of diagram

The effect of this is to divide memory, both logical (as the CPU addresses it) and physical into fixed size pages. The CPU sees what it thinks is a nicely ordered set of storage cells. In reality, these can be scattered throughout the physically addressable memory and/or stored on a hard disc.


For example:

Diagram.sixteen pages of logical memory map to eight pages of physical memory. Page zero maps to nowhere. Page one maps to physical page five. Page five maps to physical page seven. Page six maps to physical page two. etcetera. End of diagram

Enter a virtual (logical) address into the calculator using hexadecimal numbers

Physical Address Calculator
logical address 


Using the page table information

logical address virtual page physical page physical address
5000h 5 7 7000h
5001h 5 7 7001h
5123h 5 7 7123h
5FFFh 5 7 7FFFh
6000h 6 2 2000h
0561h 0 * page fault
1010h 1 5 5010h
F010h 15 0 0010h

Paging the Intel® Way

In protected mode, the 4GByte linear address space can be mapped

The address was split into 3 parts:
Diagram. Shows the application of the description given above. End of diagram

Translation Lookaside Buffer (TLB)

The CPU stores the most recently used page directory and page table entries in on-chip caches called translation lookaside buffers (TLBs).

Paging translation is performed using the contents of the TLBs. The page directory and page tables in memory are accessed only when the TLBs do not contain the translation information for a requested page.


What’s in the tables?

Diagram. Description is as follows. End of diagram
bit 0: Present flag

Indicates whether the page is currently loaded in physical memory.

When the flag is set(1), the page is in physical memory and address translation is carried out.

When the flag is clear(0), the page is not in memory and any attempt to access the page generates a page fault exception by the CPU.

When the present flag is clear for a page-table or page-directory entry, the operating system can use the other 31 bits of the entry for information about the location of the page on disk storage.

The operating system is responsible for managing virtual memory and setting or clearing the present flag.

When the CPU generates a page fault exception, the operating system invokes a page fault handler program that:

  1. Copies the page from disk storage into physical memory.

  2. Loads the page address into the page-table and sets its present flag. Other bits, such as the dirty and accessed bits, may also be set at this time.

  3. Invalidates the current page table entry in the Translation Lookaside Buffer (TLB)

  4. Returns from the page fault handler to restart the interrupted program.



bit 1: Read/write (R/W) flag

Specifies the read-write privileges for a page.

When this flag is clear(0), the page is read only; when the flag is set(1), the page can be read and written into.

bit 2: User/supervisor (U/S) flag

Specifies the user-supervisor privileges for a page. When this flag is clear, the page is assigned the supervisor privilege level; when the flag is set, the page is assigned the user privilege level.

bit3: Page-level write-through (PWT) flag

Controls the write-through or write-back caching policy of individual pages. When the PWT flag is set, write-through caching is enabled for the associated page; when the flag is clear, write-back caching is enabled for the associated page.

bit 4: Page-level cache disable (PCD) flag

Controls the caching of individual pages. When the PCD flag is set, caching of the associated page is prevented; when the flag is clear, the page can be cached.

bit 5: Accessed (A) flag

When the flag is set, it indicates that a page has been accessed (read from or written to). Memory management software clears this flag when a page is initially loaded into physical memory. The processor then sets this flag the first time a page is accessed.

bit 6: Dirty (D) flag

When the flag is set it indicates that a page has been modified.

The operating system clears the flag when a page is initially loaded into physical memory.
The CPU sets the flag when the page is accessed for a write operation.

bit 7: Page size (PS) flag

Determines the page size. This flag is only used in page-directory entries. When this flag is clear, the page size is 4 KBytes and the page-directory entry points to a page table, all the pages associated with that page table will be 4-KByte pages. When the flag is set, the page size is 4 MBytes and the page-directory entry points to a page.

bit 8: Global (G) flag

Indicates a global page when set. When a page is marked global the page-table entry for the page is not invalidated in the TLB a task switch occurs. This flag is provided to prevent frequently used pages (such as pages that contain kernel or other operating system code) from being flushed from the TLB.

The accessed and dirty flags are used by the operating system to manage the transfer of pages into and out of physical memory.


Page replacement policies.

When a page fault occurs a page is swapped from disk storage to physical memory. It may also be necessary to swap a page out of physical memory to disk storage to make room for the new page.

First-In-First-Out

Each page is 'time stamped' when it is fetched to physical memory. A list (ordered by the age) of pages currently in physical memory is maintained.

When a page fault occurs the oldest page needs to be swapped out to disk storage to make room for the new page.

A problem with this strategy is that it does not necessarily follow that because a page has been in memory a long time that it has not been used recently or is not going to be used again.

Least Recently Used

Every page is timestamped whenever it is accessed. A list (ordered by the time of the most recent access) of pages currently in physical memory is maintained.

The page that has least recently been accessed it swapped out to disk storage on the premise that if a page has been used recently it is likely to be used again.

Not Recently Used

Each page entry has an acces bit that is set whenever the page is accessed. The O/S periodically clears the access bit of all pages. This policy uses the dirty bit in conjunction with the access bit to pick the best candidate for replacement. (See other considerations below)

Other Considerations

The page replacement policy must also take into account whether or not a page has been modified (is dirty) before choosing to swap it out to disk storage.

If a page has not been modified then the copy currently residing in disk storage is identical to that in main memory and does not need to be overwritten. However, if the page has been modified then the copy on disk storage must be replaced with the modified version.

For the page in question there are four possibilities:

  1. not modified and not recently used.

  2. not modified but was recently used.

  3. was modified but not recently used.

  4. was modified and was recently used.

The best candidate for replacement is (1) and the worst candidate is (4).


Paging and Segmentation compared (briefly).

Paging Segmentation
Paging allocates physical memory in fixed size "pages". Segmentation allocates physical memory appropriate size "segments".
Any page can be put in any free place in memory. The "hole" is always exactly the right size. There may be no "hole" big enough to hold a segment, even though the total free space is enough. The free space may have become fragmented.
The last page is, on average, half full. All segments are the "right size". There is no space wasted inside the segments.

1. Phil Rice had the experience (a long time ago) of taking 15 minutes to log into a unix system that was swapping, and taking another 15 minutes to log out. The system had 8 Mbyte of RAM. Addition of another 16 Mbyte of RAM reduced the login time to under 15 seconds.

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