CSE1CT Computer Technology: Peripheral Buses

CSE1CT Computer Technology

Peripheral Busses

Introduction

It is usual practice in PCs to provide a way of adding peripheral devices to suit particular needs. There are many ways to do this, but the most flexible is to provide a communications bus via which the CPU can address and read or write the peripheral devices.

The usual practice is to use a parallel bus - one which provides a separate electrical conductor for each of the data, address and control bits.

The alternative is a "serial" bus - in which one wire carries the address and data bits one at a time. Actually parallel busses are serial too, in that they carry a sequence (in time) of things.

This lecture does not cover all busses in PCs. It could be argued that all busses are used to add peripheral devices, however the busses that are covered today have a couple of common features.

Used to connect printed circuit cards directly to the motherboard.
Connect "logically" to the CPU’s address and data bus. Often the physical connection is a little indirect.

ISA Bus

ISA = Industry Standard Architecture.
Now obsolete.

Two versions:

8 bit
16 bit

Diagram. An eight bit isa slot consists of one socket with sixty two connections. The sixteen bit socket consists of the eight bit socket with a second socket aligned with it. The second socket has thirty six connections. It carries the extra eight data bits and four address bits. End of Diagram

In the original PC, the main bus was defined by the support chips provided for the 8088 CPU - it was simply the (demultiplexed) address, data and control signals generated by the CPU.

This bus connected to a number (five I think) of expansion sockets, to memory on the motherboard and to other "on board" devices.

Diagram. CPU connects to a bus De-Multiplexer. The De-Multiplexer supplies the address, data and control busses. These busses connect to the memory and to the expansion connectors. End of Diagram

8 bit ISA Features

62 metal connectors in a tongue and groove type arrangement
8 Data Lines
20 Address lines (1 Mbyte)
4.77 MHz (4.77x10^6 cycles per second )
~2 to 8 clock cycles to transfer one byte across the bus
( 4.77 MHz * 8 bits ) /( 2 cycles) = ~2.38 Mbyte/sec maximum throughput.

16 bit ISA Bus

A 16 bit version of the 8 bit ISA bus that incorporates the original 8 bit ISA but at higher clock speed (8MHz).
Introduced when the 286 CPU was used in the AT PC.

Address lines extended to 24 bits (16 Mbytes)
Data lines 16 bits
Retains the 8 bit connector and can work with 8 bit cards.
AT clock speed of 8.33 MHz with 16 bit transfer 2 to 8 clocks/transfer gives a maximum throughput of 8.33.MBytes/second.
( 8.33 MHz * 16 bits ) /( 2 cycles) = 8.33 Mbyte/sec maximum throughput

In 386 and later computers which had ISA bus slots, a generic scheme like the next diagram showed how the slow bus was connected to the much faster CPU.

Diagram. The CPU connects to level two cache and the bus controller via a fast local bus. The bus controller connects to memory via a fast bus. The bus controller also connects to the expansion connectors through a slow input output bus. End of Diagram

Micro Channel Architecture (MCA)

Now obsolete.

With the introduction of 32-bit CPUs, the ISA bus could no longer handle the maximum throughput, only allowing for a maximum of 16-bit transfers. Rather than once again augment the ISA standard, IBM decided to create a new bus resulting in the Micro Channel Architecture or MCA bus. MCA is vastly different to ISA and is technically superior.

However, IBM in addition to replacing the ISA standard, wanted to receive royalties from companies who previously used ISA and now wanted to use MCA. This marketing tactic resulted in the development of the EISA 'Open Architecture' standard and very few non-IBM systems used the MCA bus. Another problem with the MCA architecture was that existing ISA expansion cards are not compatible.

Advantages of MCA include:

Runs asynchronously with the CPU, reducing expansion card timing problems.
Has support for bus mastering
No jumpers or switches required

Enhanced Industry Standard Architecture (EISA)

Now obsolete.

In direct response to IBM’s handling of the MCA/ISA licensing, the Enhanced Industry Standard Architecture (EISA) was created in 1988. Instead of paying IBM royalties, a number of companies went their own way and formed the EISA committee, a non-profit organisation devoted to the development of the EISA bus.

The EISA standard provided a 32-bit bus for use with the 386DX and later processors. One major advantage of EISA over MCA is that it is backwards compatible with existing ISA cards. The EISA bus adds 90 additional connectors using the same physical slot size as the 16 bit ISA slot and a two tier set of contacts.

188 Connectors
32 Data Lines
Bus speed 8.33MHz with 32 bit transfer 2 to 8 clocks/transfer gives a maximum throughput of 16.66 MBytes/second.
( 8.33 MHz * 32 bits ) /( 2 cycles) = 16.66 Mbyte/sec maximum throughput

Other advantages of EISA include:

Automatic configuration (Plug and Play)
Uses of a synchronous bus transfer protocol
Bus transfers are synchronized with the bus clock
Bus mastering

Video Electronics Standards Association (VESA) Local Bus

Now obsolete.

The Video Electronics Standards Association (VESA) Local Bus, otherwise known as VL-Bus first appeared in 1992. Like EISA, VL-Bus was created by a non profit committee specially setup to oversee the standard. This was initiated by NEC in an attempt to overcome the I/O bottlenecks affecting video adapter performance. VL-Bus allowed for access to memory at the same speed as the processor. The VL-Bus was rated with a maximum throughput of 128MB/sec to 135MB/sec, using a 32 bit data bus and a 32 bit address.

The VL-Bus was designed around the 486 control signals and the 16 bit ISA sockets. It connected connected directly to the CPU via a third "edge connector". Since the CPU was designed only to connect to a bus controller and maybe L2 cache, the VL-Bus was limited to three plug in cards.

Peripheral Component Interconnect (PCI)

In 1992 Intel headed up the creation of another industry group. Attempting to overcome the limitations of ISA and EISA, the Peripheral Component Interconnect (PCI) bus was born. Instead of directly tapping into the speed sensitive CPU bus, a set of controller chips isolated the PCI and other busses. The PCI bus is often referred to as the "Mezzanine" bus due to the additional layer it adds to the traditional bus configuration.

Data is transferred across the PCI bus at a rate of 33MHz utilising the full width of the CPU data bus. When PCI is used with a 32-bit CPU the following maximum throughput is achieved:

33MHz * 32-bits / 8 bits = 132MBytes/sec

If used with future 64-bit CPUs, transfer rates will effectively be doubled. Other advantages of PCI include:

Concurrency support (deadlock, buffering solutions)
Access arbitration (bus mastering)
Error detection and reporting
32-bit multiplexed address and data
"Processor independent" operation
Parity on address, data and command signals
Plug and Play support
188 Connectors
1 clock cycle per transfer
Bus speed 33MHz (33 x 10^6 transfers per second)

PCI Express

The latest version is a "completely different animal" to PCI.

Data is transferred in packets, rather than individually addressed pieces.
Packets are delivered via dedicated, self clocked circuits (called "lanes"). Each lane consists of a pair of conductors in each direction, providing a full-duplex circuit.
Packets contain a header with "addressing" information and data.
The "lanes" transmit at 2.5Gbit/sec, using 8b/10b encoding. Each byte is converted to a 10 bit group containing at least one logic transition, to make the code self clocking.
This results in each "lane" being able to deliver 250MByte/sec.
Individual card connectors (of different sizes) can connect 1,2,4,8 or 16 "lanes" to a card, depending on its traffic load.
Individual cards connect to the "bridge" chips via a switch. ie. PCI is no longer a bus system, it is now a switched network.

See Wikipedia™ - http://en.wikipedia.org/wiki/PCI_Express for a bit more information.

Accelerated Graphics Port (AGP)

High quality video, especially 3D requires large quantities of data to be moved between the graphics adapter and system memory. Due to the increased demands on video performance, for the likes of Graphical User Interfaces (GUI) and realistic game play, the Accelerated Graphics Port bus (AGP) was created. The AGP bus allows for high end video cards to perform operations directly on the system memory, without the need to cache locally. This significantly lowers the overhead of the PCI bus, removing all video data transfers.

The key to AGPs power and success is the high transfer rates. The first implementation of AGP, known as 'AGP 1X' ran at 66MHz, allowing for a transfer rate of 266MBytes/sec, double that of PCI. Due to improvements and refinements in the AGP standard, 2 or 4 transfers may now be performed per clock cycle, increasing throughput to 532MBytes/sec and 1.066GBytes/sec respectively. These are known as AGP 2X and AGP 4X.

Later extensions have extended this to 8 transfers per cycle (and there are rumours of 16) resulting in 2.13GByte/sec transfers.

see Wikipedia™ - http://en.wikipedia.org/wiki/Agp.

Diagram (complicated). The CPU connects to level two cache and the bridge/memory controller via the local fast bus. The bridge/memory controller connects to main memory and the AGP graphics controller via a fast bus. The bridge/memory controller also connects to the PCI bus. The PCI bus in turn connects to the Expansion Interface Controller. This last controller connects to the ISA bus, the IDE bus and the USB bus. End of Diagram